Ph.D.: Ultra Low Energy SRAM Design for Computation Intensive Wireless Sensor Nodes (Vibhu Sharma)
May 09, 2012
from 05:00 PM to 07:00 PM
|Where||ESAT, Aud. A, 00.54, Kasteelpark Arenberg 10, 3001 Heverlee|
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Ultra Low Energy SRAM Design for Computation Intensive Wireless Sensor Nodes
Medical diagnosis and health care are at the onset of a revolution fueled by improvements in smart sensors and wireless sensor networks (WSN). The computation and memory requirements of these sensor nodes grow with the increasing complexity of the signals that are being monitored. The small formfactor of the WSN nodes reduces the on-sensor battery energy and limits the amount of energy that can be scavenged. The resulting target energy consumption has to be below 100uW/cm2.
As data transmission is energy expensive, minimizing the amount of data that must be transmitted is of the utmost importance. This requires signal processing on the sensor node itself, which requires larger SRAM memories and more intelligent processors. The energy efficient SRAM design is crucial to further extend the capabilities of smart sensor nodes, as the on-chip SRAM caches consume a major proportion of the total dynamic and static energy.
Today’s memories prioritize area and speed, which are two metrics on which even the most advanced smart sensors can compromise, as even very advanced sensor nodes can get by with a speed below 100MHz. Allowing even minor compromises on area and performance provides ample opportunities to drastically reduce the static and dynamic energy consumption. This work provides a broad overview of applicable techniques, and then zooms in on several more advanced circuit level techniques for realizing energy efficient SRAMs. The techniques developed for achieving low energy SRAM includes an innovative local array design, SRAM cell design, low swing write operation and a novel variability resilient low energysense amplifier design. The presented techniques also improve the resilience against transistor variations.
In summary thesis proposes that SRAM active and static energy consumption can be drastically reduced by applying circuit techniques which prioritize energy efficiency over speed and silicon area to some extent, as validated with 2 successful silicon prototypes.
Prof. dr. ir. Wim Dehaene (promotor)
Prof. dr. Francky Catthoor (co-promotor)