COSIC seminar - A Systematic M Safe-error Detection in Hardware Implementations of Cryptographic Algorithms - Duško Karaklajić (KU Leuven)
Start date: 11/05/2012
14:00 - 15:00
Location: ESAT 00.62
This talk presents a procedure that checks whether a hardware implementation of a cryptographic algorithm is vulnerable to a specific type of fault attacks called Memory (M) safe-error attacks. It takes a Register-Transfer Level (RTL) description of a design as an input and exposes the exact timing and memory elements that are possible targets of the attack. As a proof of concept, the presented procedure is applied to a hardware implementation of the Montgomery Powering Ladder, an exponentiation algorithm commonly used in public-key cryptography.