Arish Sateesan

Research

My primary research area is FPGA design for network security. My work concentrates on the acceleration of large flow detection algorithms using configurable hardware. An algorithm-architecture co-design approach will be followed to develop novel algorithms and implementations for detecting data flows that only exceed the allowed bandwidth to a limited extent. Probabilistic data structures and approximate computing are employed to develop hardware-efficient architectures for large flow detection targeting Terabit Ethernet. The goal is to integrate the configurable hardware in network devices and demonstrate efficient and effective protection against large flow network attacks in high-speed networks.

Biography

Arish Sateesan is a Ph.D. candidate and a member of COSIC (Emerging Technologies, Systems & Security Subgroup), at KU Leuven under the supervision of Prof. Nele Mentens. He is currently working in the field of Network Security, specifically in the Acceleration of Large Flow Detection algorithms using configurable hardware(FPGA), in collaboration with the Network Security Group, ETH Zurich, on the joint research project ESCALATE.

He obtained his Bachelor’s degree in Electronics & Communication Engineering from Cochin University of Science and Technology, India in 2009. He worked as a Lecturer at College of Engineering Kidangoor during 2010-2011 and later joined Gemtech Solutions Pvt Ltd as Systems Engineer in 2011 before commencing his Master’s degree in 2013. He obtained his Master’s degree in Embedded System Design from the National Institute of Technology Kurukshetra, India. After completing his Master’s, he joined IBM as Business Intelligence Application Developer in 2015. Later he moved into academic research at Nanyang Technological University Singapore as Research Associate (Deep Learning and Embedded Systems) in 2018 prior to joining KU Leuven in 2019.

His research interests and publications lie in the fields of FPGA, network security, approximate computing, probabilistic data structures, and Convolutional Neural Networks on resource-constrained devices.